The present invention relates to monolithic semiconductor planar integrated circuit masterslice structures, and is particularly directed to a structural expedient which avoids the dielectric breakdown of the insulative layer over the semiconductor substrate during D.C. sputtering.
Planar integrated semiconductor circuit masterslices, in general, comprise an excess of active and passive components formed at the planar surface of a semiconductor member which may conventionally be a semiconductor substrate supporting an epitaxial layer containing the planar surface. The planar surface is covered by a layer of insulative material such as silicon dioxide. On the surface of the insulative layer, an excess number of contact terminals or paths are disposed in spaced relationship to each other, and there is a metallization pattern for selectively interconnecting a plurality but less than all of the excess number of contact terminals with a plurality but less than all of the excess number of components to provide a selected or tailored integrated circuit configuration. The metallization pattern is connected to the selected components in the semiconductor substrate by means of electrical contacts passing through openings in the insulative layer. Integrated circuits of this type and appropriate methods for the fabrication thereof are described in U.S. Pat. No. 3,539,876.
The contact terminals in the masterslice may conveniently have a structure such as that of the pad shown in FIG. 1P and described in Columns 17 and 18 of U.S. Pat. No. 3,539,876. In the formation of such electrical contact as well as metallization pattern of the masterslice, D.C. sputter etching or cleaning may be desirably used instead of or as a supplement to the chemical etching or cleaning steps described in Columns 17 and 18 of the above mentioned patent. For example, subsequent to the formation of the chemically etched contact terminal openings to the aluminum metallization as shown in step 4, FIG. 1P of said patent, it is desirable to utilize an additional D.C. sputter cleaning step to remove any residues or contaminants from the openings. A known and acceptable procedure for accomplishing such sputter cleaning is described in U.S. Pat. No. 3,410,774.
We have found that while D.C. sputter cleaning, such as described in U.S. Pat. No. 3,410,774, has been satisfactory when used to clean contact terminals or terminal sites which are included in the configuration and, therefore, interconnected with components by the aluminum metallization pattern, problems have arisen when the D.C. sputtering is used for excess contact terminals which are not part of the circuit configuration. In such unconnected terminals, very high electrical charge accumulations were noted which tended to exceed the dielectric breakdown strength of the material in the insulative layer. As a result, there was an often very extensive short-circuit from the unused or excess pad to the underlying substrate through the deteriorated underlying insulative layer. We found the tendency towards such shorts in only the unused or excess contact terminals despite the use of the cathodically biased mask in the procedure and structure described in U.S. Pat. No. 3,410,774.
At this point, it should be noted that even the use of an isolation pocket such as 18P in the structure described in FIG. 1P of U.S. Pat. No. 3,539,876 under the unused contact terminal will not necessarily insure against the detrimental effects of a dielectric breakdown of the insulative layer in this area.
While such an isolation pocket is capable of isolating shorts caused by pin-holes in the insulative layer as described in Column 18 of U.S. Pat. No. 3,539,876, the effects of dielectric breakdown are more massive and consequently, the short-circuits are more extensive. Such dielectric breakdown may often extend beyond the junction boundaries of the isolation pocket. This may particularly be the case when, as will be hereinafter shown, the metallization of the contact terminal extends beyond the junction boundaries of the isolation pocket. One possible solution negating the effect of dielectric breakdown would be to use larger isolation pockets so that the junctions surrounding the isolation pockets will extend beyond the limits of possible dielectric breakdown in the unused pad area or at least beyond the limits of the metallization of the contact terminal. However, such enlarged terminal isolation pockets would use up valuable "real estate" of the planar semiconductor surface which, of course, would be highly undesirable with the ever-increasing trend towards component densification in large scale integration. This would be especially true since the structure is a masterslice, and consequently, not only would the isolation pocket associated with the unused problem contact terminal have to be enlarged but the isolation pockets associated with all of the contact terminals would have to be enlarged. The reason for this being that in different circuits which may be fabricated from the masterslice, different contact terminals may end up being unused.
Accordingly, when the dielectric breakdown of the insulative layer under the contact terminal extends beyond the isolation pocket, one possible effect would be short-circuiting of other junctions in the semiconductor substrate.
In any event, one very significant undesirable effect of such dielectric breakdown in the area below the unused contact terminal has been in module package structures in which the integrated circuit chip is mounted on a dielectric substrate. Such a module package is shown in FIGS. 18 and 19 of U.S. Pat. No. 3,539,876. In this module package, the integrated circuit chip is mounted on the dielectric substrate so that all of the contact terminals which are part of the selected masterslice circuit configuration are each mounted on a conductive land on the dielectric substrate. These lands provide a conductive path to the pins in the modules. Because of the close spacing of the module lands which extend of radiate from the chip to the pins, it is often very difficult, it not impossible, for a module land to extend from a circuit contact terminal along one side of the mounted chip to a module pin beyond the opposite side of the module chip and still avoid contact with the other module lands without passing or crossing the land under the mounted chip, i.e., between the chip and the dielectric substrate. However, even when the module land is so passed under the chip, it is substantially not possible for the module land extending from the circuit contact terminal to the pin to take a path which avoids contact with at least one additional contact terminal because of the close spacing of the contact terminals in the chip. Thus, it is desirable to select such a path wherein the additional contact terminal which the land passing under the chip must touch is one of the excess contact terminal "unused" in the selected masterslice circuit configuration. When such a path is included in a module package, the previously mentioned problem of dielectric breakdown of the insulative layer under the unused contact terminal becomes very significant since a breakdown will short-circuit the entire circuit configuration to the substrate through the unused contact terminal.